A particular use of the method of this invention is in the fabrication of PNP devices. Prior art structures of this type obtain such a semiconductor using epitaxial techniques and as a result the semiconductor has been only practical of use for NPN low voltage structures. Such structures have been noted by way of U.S. Patents as exemplified by U.S. Pat. Nos. 3,226,611; 3,226,612; 3,226,613; and 3,309,245. This invention improves the art by introducing triple diffusion processes to PNP semiconductors capable of high voltage usage, i.e. V.sub.CBO = 800 volts.
The epitaxial process in so far as can be known will not provide a high resistivity P- material to enable one to manufacture high voltage devices therefrom. Prior attempts to obtain such structure for such devices has not been noted to be successful in that it has been heretofore difficult to obtain high concentration (P+) doping for a P type body of silicon. It is believed these difficulties are due to the formation of a thick glass of the impurity cooled at a different rate from the silicon and the resultant breakage of the silicon wafer (dice). Also, heretofore, it has not been easy to lap the surface without damaging the wafer. Some have sought to avoid all this by removing the glass at deposition. However, such leads to low concentration of P+ doping in the body. In addressing these problems this invention is singularly significant in advancing the art of semiconductor manufacture.